1. Field of the Invention
The present invention relates to a DLL (Delay-Locked Loop) circuit, which is a phase-locked circuit.
2. Description of the Related Art
As a result of the advances in the acceleration of processing speeds in systems that use semiconductor integrated circuit devices in recent years, memory devices have come into use such as DRAM (Dynamic Random Access Memory) and SDRAM (Synchronous DRAM) that operate at clocks of several hundred MHz. In addition, the power supply voltage has also been decreased to meet the demand for lower power consumption, and semiconductor integrated circuit devices that operate at voltages as low as 1.5 V have come into use.
In order to prevent increase in noise and malfunctioning of the system in systems such as these that operate at high speed and moreover at low voltage, it is important to suppress fluctuation in the characteristics of the output buffer circuit that is provided in the semiconductor integrated circuit device to cope with fluctuations in the power supply voltage and ambient temperature and variation in element characteristics.
In systems that include semiconductor integrated circuit devices such as DDR(Double Data Rate)-SDRAM that operate at high speed, DLL circuits, which are phase-locked circuits, are typically used to match the timing of data output of output buffer circuits that are provided in the semiconductor integrated circuit devices to the system clock. A DLL circuit is a circuit that uses an output dummy circuit having a propagation delay that is similar to the output buffer circuit to monitor the amount of delay of the output buffer circuit from the system clock, generates an internal clock for compensating the amount of delay from the system clock, and supplies the generated internal clock to the output buffer circuit, thereby synchronizing the timing of the data output of the output buffer circuit to the system clock.
We now refer to FIG. 1, which is a block diagram showing the construction of a DLL circuit of the prior art. As shown in FIG. 1, the DLL circuit of the prior art is a construction that includes:
output dummy circuit 1 having a propagation delay that is similar to that of an output buffer circuit that is provided in a semiconductor integrated circuit device;
delay element 2 for delaying a system clock (reference clock Ref) that prescribes the operation timing of the semiconductor integrated circuit device, supplying the delayed clock to output dummy circuit 1, and supplying this delayed clock as internal clock CLK; and
phase determination circuit 3 for comparing the phases of reference clock Ref and feedback signal Fb that is supplied as output from output dummy circuit 1 and supplying control signal Q for altering the amount of delay of delay element 2 based on the comparison result.
Phase determination circuit 3 compares the phases of reference clock Ref and feedback signal Fb that is supplied from output dummy circuit 1, supplies control signal Q for increasing the amount of delay of delay element 2 when the phase of feedback signal Fb is advanced from reference clock Ref, and supplies control signal Q for decreasing the amount of delay of delay element 2 when the phase of feedback signal Fb is retarded from reference clock Ref. By means of this operation, the DLL circuit operates such that the phase of feedback signal Fb that is supplied from output dummy circuit 1 matches the phases of reference clock Ref. Properly speaking, the operation of DLL circuit is controlled such that the phase of feedback signal Fb coincides with a time that is delayed one cycle from the phase of reference clock Ref.
When the phases of feedback signal Fb and reference clock Ref match, internal clock CLK is a signal having a phase that is advanced from that of feedback signal Fb by exactly the propagation delay of output dummy circuit 1, and that is also advanced from the phase of reference clock Ref by exactly the propagation delay of output dummy circuit 1. Using internal clock CLK to operate the output buffer circuit therefore causes data signals to be supplied as output from the output buffer circuit with the same phase as reference clock Ref.
We next refer to FIG. 2, which is a circuit diagram showing an example of the construction of the phase determination circuit shown in FIG. 1, and FIG. 3A and 3B, which are timing charts showing the operation of the phase determination circuit shown in FIG. 1.
As shown in FIG. 2, phase determination circuit 3 is a construction that includes: two first flip-flops 311 and 312 to which reference clock Ref is applied as input; and second flip-flop 32 to which the output of first flip-flops 311 and 312 is applied as input and that generates control signal Q (phase determination result) and the inverted signal Qb of this control signal Q for controlling the amount of delay of the above-described delay element 2. First flip-flops 311 and 312 and second flip-flop 32 are each made up from two NAND gates, the output of each NAND gate of a pair being fed back as input to the other NAND gate. Power supply voltage VDD and feedback signal Fb are applied as input to one of the NAND gates of first flip-flop 312. The input capacitance of each NAND gate to which reference clock Ref and feedback signal. Fb are applied is set to substantially the same value.
In a construction of this type, when reference clock Ref and feedback signal Fb are both “LOW” and feedback signal Fb becomes “HIGH” before reference clock Ref, as shown in FIG. 3A, a “LOW” signal is supplied as control signal Q. On the other hand, when reference clock Ref and feedback signal Fb are both “LOW” and reference clock Ref becomes “HIGH” before feedback signal Fb as shown in FIG. 3B, a “HIGH” signal is supplied as control signal Q. The delay amount of delay element 2 is controlled based on these phase determination results. FIGS. 3A and 3B show a case in which the phases of reference clock Ref and feedback signal Fb are compared with the rising edge of feedback signal Fb as the standard, but the phases may be compared with the rising edge of reference clock Ref as standard, or the phase comparison may be realized with the falling edge of either reference clock Ref or feedback signal Fb as the standard.
We next refer to FIG. 4, which is a circuit diagram showing an example of the construction of the delay element that is shown in FIG. 1. In addition, FIG. 5 is a circuit diagram showing an example of the construction of the delay chain circuit that is shown in FIG. 4, and FIG. 6 is a circuit diagram showing an example of the construction of the CLK mix circuit that is shown in FIG. 4. FIG. 4 is a construction typically referred to as a digital delay element.
As shown in FIG. 4, delay element 2 is a construction that includes: delay chain circuit 21 for supplying signals in which reference clock Ref has been delayed in steps at relatively large time intervals; and delay amount interpolation circuit 22 for interpolating the delay amount of each step that is supplied from delay chain circuit 21.
As shown in FIG. 5, delay chain circuit 21 is a construction that is provided with: a plurality of inverter circuits connected in a series, and output ports (1, 2, 3, . . . , N, N+1, N+2, . . . , Nmax; where N is a positive integer), one output port being provided for each two inverter circuits. In a construction of this type, reference clock Ref is delayed by each of the inverter circuits, and, reference clock Ref is supplied as output from each output port, the amount of delay of this reference clock Ref depending on the number of inverter circuits that are inserted between that output port and the input port of reference clock Ref. In this case, the amount of delay realized by two inverter circuits (the difference in delay amount between adjacent output ports) is on the order of 400 ps. Delay element 2 that is shown in FIG. 4 is a construction that selects the output signals (M and M+1, where M is a positive integer) of two consecutive output ports of the output ports of delay chain circuit 21 and interpolates the amount of delay between these output signals by means of delay amount interpolation circuit 22.
As shown in FIG. 4, delay amount interpolation circuit 22 is a construction that includes:
CLK selection circuit 23 for selecting, in accordance with control signal Q, the output signals (M and M+1) of two output ports of the output ports of delay chain circuit 21 having consecutive delay amounts;
antiphase CLK generation circuit 24 for supplying as output the output signals (M and M+1) of CLK selection circuit 23 and the inverted signals of these signals (Mb and (M+1)b);
CLK mix circuit 25 that is supplied with the output signals of antiphase CLK generation circuit 24 for interpolating the delay amounts of the two output signals (M and M+1) that have been selected by CLK selection circuit 23;
bias circuit 26 for generating bias voltages for altering the delay amounts produced by CLK mix circuit 25 in accordance with control signal Q; and
CMOS circuit 27 for converting the output signal of CLK mix circuit 25 to CMOS voltage levels.
As shown in FIG. 6, CLK mix circuit 25 is a construction that includes:
transistor Tr1 that receives output signal (M) of CLK selection circuit 23;
transistor Tr2 that receives antiphase clock (Mb) that is supplied from antiphase CLK generation circuit 24 and that has its source connected in common with the source of transistor Tr1;
transistor Tr3 that receives output signal (M+1) of CLK selection circuit 23;
transistor Tr4 that receives antiphase clock (M+1)b that is supplied from antiphase CLK generation circuit 24 and that has its source connected in common with the source of transistor Tr3;
first current-source transistor Tr5 for causing a prescribed current to flow to transistors Tr1 and Tr2; and,
second current-source transistor Tr6 for causing a prescribed current to flow to transistors Tr3 and Tr4.
The drains of transistors Tr1 and Tr3 are connected in common and are supplied with power supply voltage VDD by way of resistor R1. Similarly, the drains of transistors Tr2 and Tr4 are connected in common and supplied with power supply voltage VDD by way of resistor R2. Transistors Tr1 and Tr2 make up one differential circuit, and transistors Tr3 and Tr4 make up another differential circuit. Output signal OUTb is supplied from the drains of transistors Tr1 and Tr3, and output signal OUT is supplied from the drains of transistors Tr2 and Tr4.
CLK mix circuit 25 that is shown in FIG. 6 is a construction that uses two differential circuits to mix output signals (M)/antiphase clock (Mb) and output signals (M+1)/antiphase clock (M+1) in order to generate output signals OUT/OUTb having a desired delay amount. CLK mix circuit 25 changes the delay amount of output signals OUT/OUTb by altering the bias voltages that are supplied to first current-source transistor Tr5 and second current-source transistor Tr6. As an example, if Ia is the current that flows to first current-source transistor Tr5 and Ib is the current that flows to second current-source transistor Tr6, Ia+Ib is always fixed, and if the bias voltages are then varied to obtain Ia:Ib=10:0; then output signals OUT/OUTb will be a clock having a delay amount that is delayed from output signal (M)/antiphase clock (Mb) by just one differential circuit stage. If the bias voltage is varied to obtain Ia:Ib=0:10, output signals OUT/OUTb will be a clock having a delay amount that is delayed from output signal (M+1)/antiphase clock (M+1)b by one differential circuit stage. Further, if the bias currents are varied to obtain Ia:Ib=5:5, output signals OUT/OUTb will be a clock having a delay amount that is the midpoint of output signal (M)/antiphase clock (Mb) and output signal (M+1)/antiphase clock (M+1)b.
CLK selection circuit 23 is constructed from, for example, a DSP (Digital Signal Processor) that includes a multiplexer. CLK selection circuit 23 serves the purpose of selecting prescribed output signals of delay chain circuit 21 in accordance with control signal Q and antiphase determination signal R (to be described hereinbelow). In addition, bias circuit 26 is constructed from, for example, a DSP that includes a D (Digital)/A (Analog) conversion circuit and serves the purpose of supplying prescribed bias voltages in accordance with control signal Q.
A delay element that is included in the above-described DLL circuit of the prior art is provided with characteristics for increasing the delay amount at a prescribed inclination in accordance with the phase difference between feedback signal Fb and reference clock Ref, as shown in FIG. 7A. Operation of this type is similar to a construction in which the delay element is of the analog type.
In an actual delay element, however, fluctuations in the ground potential or factors relating to the circuit configuration may cause time intervals in which the delay amount decreases (or the delay amount remains unchanged) as the phase difference increases or in which the delay amount increases (or the delay amount remains unchanged) as the phase difference decreases, as shown by “D” in FIG. 7B.
This type of nonlinear characteristic is caused by, for example, increases in the ground potential that result from the flow of a large amount of current to the ground potential at the falling edge of internal clock CLK that is supplied to all output buffer circuits in a semiconductor integrated circuit device.
When the ground potential rises, the power supply potential that is supplied to delay chain circuit 21 decreases substantially, and the delay time of the inverter circuits that make up the delay chain circuit 21 increases. In addition, current Ia that flows to the first current source transistor Tr5 in CLK mix circuit 25 and bias voltage BiasA that is applied to the gate of first current-source transistor Tr5 have the relation:Ia∝(BiasA)2
and current Ib that flows to second current-source transistor Tr6 and the bias voltage BiasB that is applied to the gate of second current-source transistor Tr6 have the relation:Ib∝(BiasB)2
As a result, fluctuations in the bias voltage due to rises in ground potential have a strong influence on output signals OUT/OUTb.
When phases are compared with the rising edge of feedback signal Fb as the standard, reference clock Ref is “HIGH” in the state shown in FIG. 8A, and the phase determination circuit therefore supplies a determination result for advancing feedback signal Fb (Direction E in FIG. 8A). However, when the characteristic of delay element is in an interval indicated by “D” in FIG. 7B, a reduction of control signal Q for advancing feedback signal Fb causes the delay amount to increase. This increase in the delay amount causes operation in the DLL circuit that retards feedback signal Fb (Direction F in FIG. 8A).
In the state shown in FIG. 8B, in contrast, reference clock Ref is “LOW”, and the phase determination circuit therefore supplies a determination signal for retarding feedback signal Fb (Direction F in FIG. 8A). However, if the characteristic of the delay element is in an interval indicated by “D” in FIG. 7B, increasing control signal Q to retard feedback signal Fb instead causes a reduction of the delay amount, and the operation of the DLL circuit therefore advances feedback signal Fb (Direction E in FIG. 8B).
The problem therefore occurs that, when the characteristic of the delay element is in an interval indicated by “D” in FIG. 7B, reference clock Ref and feedback signal Fb enter an antiphase state and cannot escape from this state (enter a locked state). In such a case, the data signals that are supplied as output from the output buffer circuit using internal clock CLK are shifted one-half cycle with respect to reference clock Ref and are therefore defective.